This invention pertains generally to the field of power transistors and, more particularly, to push-pull power transistor devices.
With the considerable recent growth in the demand for wireless services, such as personal communication services, the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz frequencies. At such high frequencies, laterally diffused, metal oxide semiconductor (LDMOS) transistors have been preferred for power amplification applications, e.g., for use in antenna base stations.
Efficiency is always a major consideration when designing RF power amplifiers. Using a push-pull topology produces an amplifier with higher efficiency than a single ended design operating at comparable power and frequency levels. The two transistors in a push-pull amplifier design are operated 180 degrees out of phase. An important factor for stable operation of such high power, high frequency devices is providing a uniform ground reference potential for both of the power transistors and the surrounding circuitry. In particular, high power, high frequency power transistor devices control relatively large amounts of current. Because of the ground path losses for these currents, there is a voltage drop created, which causes signal loss, decreased efficiency, and reduced isolation between ports, which in turn reduces stability. These high currents and high voltages require that special considerations be given to the physical design of the power transistor devices and their physical integration into an amplifier system.
In order to take advantage of the desirable attributes associated with the push-pull amplifier, the characteristics of the two transistors must be quite similar. This is addressed in present day implementations by manufacturing a push-pull transistor package, which contains two transistor dies with two gate regions, two source regions and grounding of the transistor drain regions through the flange. Similarity of the two transistors is ensured by selecting transistor dies that are adjacent to each other on the wafer. This is a cumbersome and expensive task. In spite of this effort to select similar transistors, when packaged, inaccuracies associated with placement of the individual devices causes the two transistors to behave somewhat differently, degrading performance. In addition, the transistors must be placed at some minimum distance from each other. This physical separation of the device grounds degrades performance as a result of an introduction of common lead currents.
By way of example, FIG. 1 illustrates a prior art push-pull transistor package 15. A first LDMOS transistor chip (or xe2x80x9cdiexe2x80x9d) 10 is attached to a conductive mounting substrate (or xe2x80x9cflangexe2x80x9d) 28 in close proximity to a second LDMOS transistor die 20, which is also attached to the flange 28. (As used herein, xe2x80x9cchipxe2x80x9d and xe2x80x9cdiexe2x80x9d are synonymous). A first input (gate) lead 12 is attached to, but electrically isolated from, the mounting flange 28. The first input lead 12 is electrically connected (using a well known wirebond technique) to a gate region of the first transistor die 10. A second input (gate) lead 22 is attached to, but electrically isolated from, the mounting flange 28 adjacent the first input lead 12. The second input lead from 22 is electrically connected to a gate region s of the second transistor die 20. A first output (drain) lead 14 is attached to, but electrically isolated from, the mounting flange 28 and electrically connected to a drain region of the first transistor die 10. A second output (drain) lead 24 is attached to, but electrically isolated from, the mounting flange 28 adjacent the first output lead 14, and electrically connected to a drain region of the second transistor die 20. Common element (source) regions located on the undersides of the first and second transistor dies 10 and 20 are directly connected to the mounting flange 28, such that the flange 28 acts as a combined support structure, heat sink, and ground reference.
Present day LDMOS transistors use a heavily doped sinker region for grounding the source region of the transistor to the flange. By way of illustration, FIG. 2 is a side view of a LDMOS transistor die 30, which is representative of transistor dies 10 and 20 in the package 15 of FIG. 1. The transistor die 30 includes an input (gate) region 34, output (drain) region 33, and common element source region 35 formed on a semiconductor (e.g., silicon) die 32, which is shown attached to a metal mounting flange 28. A heavily doped sinker region 36 forms a electrical conduction path for the common element current from the source region 35, through the die 32, to the flange 28, which represents a ground reference for the transistor device 30. The sinker region 36 is typically formed by extensive diffusion after a high dosage implant on the top side of the transistor device 30. In particular, the sinker region 36 provides a common element current path having a minimal resistance and low inductance. Present day transistors for such applications use a large epitaxial region of about nine microns in thickness for supporting high breakdown voltages. The associated lateral diffusion in the sinker region can occupy as much as seven microns. This corresponds to about half of the total width of the transistor, and consequently increases the die size.
In accordance with one aspect of the invention, a more optimal performance of a push-pull RF transistor device is achieved by fabricating both transistors in an interdigitated fashion on a single semiconductor die.
In one embodiment, a push-pull transistor device comprises a single chip having first and second transistors formed thereon and configured for push-pull operation, the first and second transistors sharing a common element current region. In some embodiments, the first and second transistors each have a plurality of conduction regions, each conduction region formed by adjacent gate and drain regions of the respective transistor, wherein conduction regions of the first transistor are interleaved with conduction regions of the second transistor.
In another embodiment, a push-pull transistor package comprises a mounting substrate providing a combined support structure and common element ground reference. A single chip having first and second transistors formed thereon and configured for push-pull operation is attached to the mounting substrate, the first and second transistors sharing a common element current region. A conductor, e.g., one or more bond wires, electrically connects the shared common element current region to the mounting substrate.
In alternate embodiments, a low resistance doped path through the device may be used to electrically connect the shared common element current region to the mounting substrate. Also, in alternate embodiments, the common element ground reference may be different than the mounting substrate for the chip, in which case the conductor electrically connects the shared common element current region to the actual ground reference.
Other aspects and features of the invention will become apparent hereinafter.